; JED2EQN -- JEDEC file to Boolean Equations disassembler (Version V063)
; Copyright (c) National Semiconductor Corporation 1990-1993
; Disassembled from IPI-U01.jed. Date: 2012-10-28

; The Request To Send line on serial channel 1 is controlled by a latch in PAL IC1.
; A read or write operation to each I/O address produces the actions below:
; A4 = 
;	0060	+12V on RTS1 (PL4 pin 7)	; see a latch in PAL IC1
;	0070	-12V on RTS1

chip IPI-U01 PAL20L10

cpu_a16	=1	;
cpu_a15	=2	;
cpu_a14	=3	;
cpu_a13	=4	;
cpu_a12	=5	; pin 2 of RAM
cpu_a6	=6	; pin 4 of RAM
cpu_a5	=7	;
cpu_a4	=8	;
/IORQ	=9	; not an address line
/MREQ	=10	; not an address line
GND	=12	;

/RD	=11	; connection on my board, not used in equations.
/WR	=13	; connection on my board, not used in equations.

/ROM_pin_20	=14	; EPROM pin 20 = 
/RAM_pin_20	=15	;
/U8_pin_19	=16	; Application connector data buffer enable
/FIFO_pin_36	=17	;
/RTS1			=18	; pins 9 and 10 of 14C88 control RTS1
/RTS1_mark		=19	;
/RTS1_complement	=20	;
/RTS1_space		=21	;
VCC	=24	;


equations

cpu_a16_to_a12_are_00000	=	/cpu_a16 * /cpu_a15 * /cpu_a14 * /cpu_a13 * /cpu_a12
cpu_a16_to_a13_are_0111		=	/cpu_a16 *  cpu_a15 *  cpu_a14 *  cpu_a13
;
; Some kind of cross-coupled NAND gates?
;
RTS1		=	/RTS1_mark	*	/RTS1_complement
RTS1_complement	=	/RTS1_space	*	/RTS1
;
; I/O device decoding.
; Address lines A12 and above are low.
;
;
FIFO_pin_36	=	cpu_a16_to_a12_are_00000	*	cpu_a6	*	/cpu_a5	*	/cpu_a4	*	IORQ	; a6,5,4 = 100 = 0040

RTS1_space	=	cpu_a16_to_a12_are_00000	*	cpu_a6	*	 cpu_a5	*	/cpu_a4	*	IORQ	; a6,5,4 = 110 = 0060	+12V on RTS1 (space)
RTS1_mark	=	cpu_a16_to_a12_are_00000	*	cpu_a6	*	 cpu_a5	*	 cpu_a4	*	IORQ	; a6,5,4 = 111 = 0070	-12V on RTS1 (mark)

;
; U8 is an LS245 data buffer to PL2, the Applications connector.
; Enables top 8K of the 64K space, the manual says Fxxx is reserved.
;
U8_pin_19	=	cpu_a16_to_a13_are_0111	*	IORQ		; 0Exxx, 0Fxxx
		+	cpu_a16_to_a13_are_0111	*	MREQ		; 0Exxx, 0Fxxx

;
; Decodes 128K spaces each for ROM and RAM, with a 16K gap in the RAM
;
ROM_pin_20	=	/cpu_a16	*	/cpu_a15				*	MREQ	; lowest 32K space

RAM_pin_20	=	 cpu_a16							*	MREQ	; 10000h = high 64K
		+				 cpu_a15	*	/cpu_a13	*	MREQ	; 
		+				 cpu_a15	*	/cpu_a14	*	MREQ	; 08000h = third 16K

;
; A16 15 14 13
;   1  x  x  x
;   0  1  0  x
;   0  1  x  1
;   0  1  1  0	RAM disabled here  
;


/RTS1_space.oe	=	vcc
/RTS1_complement.oe	=	vcc
/RTS1_mark.oe	=	vcc
/RTS1.oe	=	vcc
/FIFO_pin_36.oe	=	vcc
/U8_pin_19.oe	=	vcc
/RAM_pin_20.oe	=	vcc
/ROM_pin_20.oe	=	vcc